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Section 10 provides application notes and briefs for engineers and engineering managers who seek practical ways to reduce design costs, improve design quality, and shorten design cycles.

This section also shows all EPLD package outlines, describes thermal characteristics of EPLDs, explains how to select sockets for Jlead packages, and lists Altera sales offices, representatives, and distributors. Phone numbers and addresses of Altera Sales Offices, Representatives, and Distributors are listed at the end of this data book. These devices allow engineers to electrically program standard, off-the-shelf logic elements to meet the specific needs of their applications.

Proprietary logic functions can be designed and fabricated in-house, eliminating the long engineering lead times, high tooling costs, complex procurement logistics, and dedicated inventory problems associated with custom Application-Specific Integrated Circuit ASIC devices, such as gate arrays and standard cells. Altera provides the broadest line of CMOS EPLDs in the industry, with products ranging in density from hundreds to thousands of gates, offered in a variety of packages with 20 to pins.

These EPLDs, together with Altera development software, enable system manufacturers to create custom logic functions for a wide variety of applications. See Figure 1. Figure 1. EPLDs are also valuable for prototyping high-density custom devices, which enables designers to test markets and evalua te systems before committing to expensive engineering development cycles and tooling charges.

Altera concentrates on creating high-performance device architectures and easy-to-use, highly productive CAE software. Altera products meet the demands of designers who require complete solutions to logic integration that include both PAL speed and FPGA density. See Figure 2. Figure 2.


PLD Speed vs. EPLD families are divided into two architectural categories: the first provides maximum flexibility for generalpurpose logic replacement; the second is specialized for performing specific system design tasks.

The EP-series architecture includes to pin EPLDs that feature zero-standby power, propagation delays tpo of 12 ns, and counter frequencies of up to MHz. Altera is also developing the next generation of EPLDs-the EPM series-that will provide integration densities of 1, to 20, gates, with additional increases in system speed. EPS-series EPLDs offer the logic and speed required for complex control logic, state machines, and imaging and display applications.

EPLDs are available in windowed erasable ceramic packages for development, or one-timeprogrammable plastic versions for high-volume production requirements. Software Tools Altera software products are developed together with the EPLD architectures, so features are placed where they are most appropriate-in either software or hardware. The result is efficient software tools that offer familiar design entry methods and rapid design com pletion.

See Figure 3. With Altera's CAE development tools, users can take a logic circuit from design entry to device programming in a matter of hours.


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